AESIP: Arch-aware ASIP-ISA Co-Design via Program Synthesis
A hardware-software co-optimization framework for efficient ASIP design using e-graphs, program synthesis, and equality saturation.
Portfolio
Mozart: Chiplet Ecosystem-Accelerator Codesign Framework
A novel framework for designing composable, heterogeneous chiplet-based neural network accelerators with systematic design space exploration.
Minimum Area Retiming for xSFQ Logic
Linear programming formulation for simultaneous register and duplication logic minimization in superconducting circuits.
Mixed Circuit of Binary & Stochastic Computing
Domain-specific language and code generation framework for agile development of mixed binary-stochastic circuits.
Machine Learning for High Level Synthesis
Graph Neural Network-based approach for accurate and fast prediction of HLS metrics with feature extraction from reports.
Recommendation System for Big Data
Scalable recommendation system implementation using Hadoop cluster with Spark and MapReduce for distributed computing.
Multi-threaded SQL Database
Custom database implementation with SQL-like syntax supporting multi-threading, thread pools, and parallel processing.
Scheduling Algorithm in Minix 3.2.1
Kernel-level implementation of advanced scheduling algorithms including Earliest Deadline First and Lottery scheduling.