AESIP: Arch-aware ASIP-ISA Co-Design via Program Synthesis, Equality Saturation, and External Don’t Cares
Published in ISCA 2026 (Under review), 2026
We propose AESIP, a hardware-software co-optimization framework for efficient ASIP design that leverages e-graphs, program synthesis, and don’t care-based hardware optimization to achieve up to 29.7% area reduction.
Recommended citation: Haoran Jin, Nathaniel Bleier. AESIP: Arch-aware ASIP-ISA Co-Design via Program Synthesis, Equality Saturation, and External Don't Cares. ISCA 2026 (Under review).
